Field of the Invention
The present invention relates in general to charge pump configurations, and more particularly to a self clocking comparator for providing pump clocks to drive a charge pump.
Description of the Related Art
In order to perform useful functions at a normal chip current level (e.g., on the order of microamperes, μA), it is sometimes useful to generate a voltage larger than the highest supply voltage provided to the chip. This is especially true when the minimum specified supply voltage for the part is quite low. The supply voltage may be as low as 1 to 2 Volts (V), such as, for example, about 1.6 Volts (V). A charge pump can generate a voltage larger than the supply voltage, but it is challenging to operate one efficiently at low current levels (e.g., in the nanoampere (nA) range).
A charge pump may use switched capacitors to generate a voltage higher than the supply voltage. A digital clock is needed to control the phases of switches connecting capacitors between ground (GND, or VSS), the supply voltage (e.g., VDD), an output voltage, and/or any other potential levels. The generated voltage can be controlled either by continuously switching or pumping the capacitors and regulating the resulting voltage down to the desired level, or by only pumping as needed such as by gating a separate pump clock that controls the capacitor switching and directly using the switched capacitor output.
A comparator regulates the charge pump output by monitoring and comparing the output to a desired level and generating a digital signal. The use of the charge pump output voltage generally draws current from the developed voltage. To keep the output at the desired level, the charge pump has to be able to provide this current. The frequency that the capacitors can switch multiplied by the size of those capacitors is proportional to the current that can be provided.
The comparator has some delay so that when the inputs cross each other such that the output of the comparator is expected to change, there is some delay in time before the comparator output does, in fact, change. In the classic configuration where the comparator output gates an independent clock source, at some point the output rises above the desired level and continues rising for a period of time related to the delay through the comparator. This voltage excursion is related to the capacitor switching frequency multiplied by the size of the capacitors so it is proportional to the maximum current that can be provided by the charge pump. If the voltage excursion is too large, the charge pump output tends to oscillate back and forth causing the control loop to unstable or nearly unstable. This imposes a limit on how much delay can be tolerated in the comparator to support a given amount of current out of the charge pump. The delay requirement in the comparator determines the current that may be consumed in the comparator.